Xilinx to Demonstrate Smarter Network Packet Processing Solutions at Linley Processor Conference 2013

Xilinx, Inc. will highlight its All Programmable packet processing solutions for next-generation Smarter Networks at the Linley Processor Conference, October 16-17, in Santa Clara, CA. Xilinx technology experts will present and demonstrate solutions that enable full line card data path services.

Xilinx packet processing solutions empower system developers to shorten design cycles, while meeting rapidly changing connectivity standards, targeting the growing ASIC and ASSP gaps for next-generation Smarter Networks.

Xilinx Participation at Linley Processor Conference 2013

• Presentation by Mark Gustlin, Principal System Architect
  "Enabling Data Path Services via Multidimensional Programmable Solutions"
  This presentation will discuss next-generation line card requirements for power-to-performance optimized solutions and unified data-path services that scale to multi-hundred gigabits-per-second. The presentation will provide details on the Xilinx unified packet processing methodology for delivering Xilinx's network optimized SmartCORE™ IP solutions that employ All Programmable devices directly in the data path of a line card. This complete solution encompasses front panel interfaces, packet parsing, integrated search and packet editing, and hierarchical traffic management.
• Technical Demonstration
  Programmable Data Path Processor Solution – Demonstration showcases full interface line rate running on a Xilinx Virtex^®-7 All Programmable FPGA. The dynamically re-programmable packet processor SmartCORE IP enables hitless in-service program updates at a speed of 150 million packets per second without service interruptions.
• Technical Showcase
  Technical Showcase #1 - This demonstration showcases a Virtex-7 All Programmable FPGA line card with granular per flow traffic manager running at 80Gbps line rate – parameterized TM architecture with dynamic control of shaping, policing and congestion control based upon Xilinx SmartCORE IP.
  Technical Showcase #2 - Based upon Xilinx SmartCORE IP, this demonstration showcases a Zynq^®-7000 All Programmable SoC implementation of a standalone 12-tuple search engine enabling OpenFlow classification with extended programmable packet processing search depth and throughput capabilities and scalability across interface line rates.