Low-noise Instrumentation Amplifier for Sensor Devices

Dr. Ippei Akita, Department of Electrical and Electronic Information Engineering, Toyohashi University of Technology, talks to AZoSensors about the design and development of a low-noise instrumentation amplifier for sensor devices.

Why are low-noise instrumentation amplifiers critical components of arrayed sensor devices?

Instrumentation amplifiers (IAs) act as an interface between physical sensors and information we want. Today, we can find a lot of sensors in our life, such as cars, smart phones, or home security systems. Moreover, such sensors are increasing in number and this will bring us with more comfortable living.

On the other hand, in a field of neuroscience, neural probe array devices with high-spatial resolution, ~100-um pitch, have been developed and proposed from several institutions, including Toyohashi Probe from Toyohashi Tech., in order to analyse a mechanism of brain. So, such arrayed sensor devices needs arrayed low-noise IA system. Of course, such sensors output a weak electrical signal which is nearly comparable with physical and electrical noise, and thus appropriate amplification is needed for acquiring information we want.

Furthermore, each amplifier in such arrayed IA system has to be small size and low-power consumption because many IA channels are integrated on a chip. So, development of low-noise IA in a small silicon die area is highly necessary.

How does this novel, smaller-sized integrated circuit chip work; what does the technique involve?

For realizing small-size IA, I came up with an idea using A “digitally-assisted analog technique” for reducing an offset voltage of the IA. In conventional IAs, a large chip area is needed for suppressing such offset voltage. The proposed novel technique can enable small area realization of IA without an increase of chip area.

When a weak signal is amplified, we have to define a reference potential for the signal, generally the ground one. So, a differential amplifier is needed like well-known operational amplifiers (opamps).

If an offset voltage, which comes from production tolerance of IA chip, exists between the differential input terminals, the input weak signal with offset voltage are amplified together, resulting in a clipping (distortion) of the desired signal. This is a problem in a signal processing chain because of a lack of information.

Although some conventional IAs utilize a filter to suppress such offset voltage, this requires a large chip area. The proposed digitally-assisted technique to reduce such offset voltage is based on a reconfigurable input device of IA.

In this technique, differential input devices of IA are divided to some parts and they are swappable between two input terminals. Of course, since each divided device has offset voltage independently, total offset voltage between the two terminals is the same with the non-divided case.

However, each divided device can be reconfigured for minimizing the total offset voltage. This results in small offset IA without chip area overhead compared with the conventional approach.

One design issue is how to detect the offset and to search for the best combination in the calibration. One may imagine that such detector and functional blocks will be more complicated because it needs an accurate analog-to-digital converter.

In the designed IA, a simple digital signal processor and a sophisticated algorithm can easily realize the calibration in a chip, resulting in area-efficient realization. Therefore, a key point of the implemented IA system is that “a digital signal processing helps an imperfect aspect of an analog signal processing.”

Although an analog signal includes a lot of information compared with a digital one, it is difficult to handle it. Therefore, a concept of digitally-assisted analog circuit is important in recent analog integrated circuit design (Figure 1).

Figure 1. The above figure shows an example of a conventional IA with offset voltage. It is assumed that the top-side amplifier (red triangle) has an offset of 0.4 and the bottom-side amplifier (blue triangle) does that of -0.5. They are not matched. In this case, one is connected to a reference level, and a weak signal is input to the other. The total offset is 0.4-(-0.5)=0.9, and thus the desired signal and this offset are amplified together, resulting in a clipped (or distorted) output signal, which means a lack of information. Image Courtesy of Dr. Ippei Akita, Department of Electrical and Electronic Information Engineering, Toyohashi University of Technology, Toyohashi, Japan.

What are the main applications for small instrumentation amplifiers (IA)?

Our small IA chip is usable in several arrayed sensor devices. As described above, one of most usable application is for neural arrayed probe. Another application may be for bio-chemical sensor array technology.

Of course, it is also used for instrumentation for consumer electronics (as a low cost component), such as battery monitoring systems, temperature sensor, or some front-end circuits for sensor devices.

Can you explain how you implemented the IAs?

First, I came up with the idea of a circuit solution how to minimize the size of IA with low noise and low power. Then, I put some circuit elements, transistors or resistors, on a pallet of CAD tools, and I verified that the IA circuit with my idea can work correctly and meet the specification by using circuit simulators, such as the SPICE-based one.

After I finished designing the IA circuit, I drew a physical layout for mask pattern and the complete design data was submitted to a silicon chip foundry. The prototype chip has been fabricated in a standard 0.18-um CMOS technology, which is not an expensive process and well-used technology for consumer products. (low-cost!)

Figure 2. This figure shows the proposed IA with the reconfigurable input devices. The left figure is an example that two input devices are divided into three parts, respectively. In this case, it is noted that the total offsets for each divided device are the same with those for each non-divided one; {0.2+(-0.1)+0.3}-{-0.4+0.1+(-0.2)}=0.4-(-0.5)=0.9. Furthermore, each divided device is swappable between two input terminals. Therefore, as shown in the right figure, this reconfigurable device provides a suppression of offset voltage by searching for the best combination. In this example, the total offset is significantly reduced to {-0.1-0.2+0.3}-{-0.4+0.1+0.2}=0-(-0.1)=0.1. Image Courtesy of Dr. Ippei Akita, Department of Electrical and Electronic Information Engineering, Toyohashi University of Technology, Toyohashi, Japan.

Are there any limitations to this technology and how do you plan on facing such challenges?

One of the limitations is that the calibration process searching for the best combination needs some time - a few milliseconds - before a normal signal processing mode, though this foreground calibration might be not acceptable in some applications. Therefore, a fast calibration method is required for such applications.

How will this technology benefit the end-user?

I believe that breakthrough for brain function by using my developed small IA system will bring significant benefits to us in the view of medical care (point of care), drug development, and a progress of brain machine interface (BMI). Furthermore, such high-performance devices will be used in the field of consumer electronics for making our living more comfortable.

How do you plan on developing this technology further?

As a next step, now we are developing an arrayed IA system based on this technology. Moreover, other functions, such as analog-to-digital converters and some signal processing unit, will be included and a “trick” for efficiently conditioning a lot of information will be implemented on a chip. We are thoroughly studying the new idea, “trick,” which will provide an ultra-low power realization.

Where can we find further information on your project?

You can find more technical details in the International Solid-State Circuits Conference (ISSCC; it is often said as the Olympic of semiconductor) digest of technical paper entitled “A 0.06mm² 14nV/√Hz chopper instrumentation amplifier with automatic differential-pair matching.”

About Dr. Ippei Akita

Ippei Akita received the B.E., M.E., and Ph.D. degrees in Electronic and Information Engineering from Toyohashi University of Technology, Toyohashi, Japan, in 2003, 2005, and 2008, respectively.

In 2008, he joined the Wireless System Laboratory, Corporate Research and Development Center of Toshiba Corporation, Kawasaki, where he engaged to develop AD/DA converters and opt-electronic integrated circuits (OEICs) for wireless/wireline communication systems.

Since April 2011 he has been with the Department of Electrical and Electronic Information Engineering, Toyohashi University of Technology, Toyohashi, where he is now an Assistant Professor. His current research interests include high-speed high-resolution data converters, mixed-signal integrated circuits, RF circuits, and low-power analog front-end circuits for biomedical instrumentation.

Dr.Akita is the recipient of the 2006 IEEJ International Analog VLSI Workshop Best Paper Award. He is a member of the IEEE (SSCS, CASS, and IMS) and the IEICE (C).