Dec 21 2012
European funded project investigates advanced countermeasure techniques to compensate the dramatic variability device phenomena on Embedded Memories for future technologies.
The Seventh Framework Program for Research and Technological Development funded European project TRAMS (Tera-scale Reliable Adaptive Memory Systems, www.trams-project.eu) investigates the impact of the statistical variability on tera-scale embedded SRAM and DRAM memories based on sub 16 nm technology generations when using planar bulk, 3D-FinFET, Carbon Nanotubes and III_V/Ge technologies. The Universitat Politècnica de Catalunya · BarcelonaTech (UPC) leads the project.
The statistical variability introduced by the discreteness of charge and matter has become a major obstacle to scaling and integration. The impact of this statistical variability on embedded memories is particularly dramatic, by slowing supply voltage scaling, especially for SRAM and DRAM, and threatening the continuation of area scaling that helps drive integration targets for Systems on Chip.
The consortium of the TRAMS project has investigated on the implementation of efficient countermeasure techniques oriented to tolerate these limiting phenomena in order to produce robust circuits that keep the technology progress trend. New adaptive, mechanisms have been investigated and evaluated for different levels of variability.
Run-time adaptability has been granted through novel two level mechanisms. The first level consists of sensors placed within the memory; and the second level reconfigures dynamically the memories based on the sensor data in order to meet the performance and power targets.
Original memory variability-aware pro-active adaptable structures have been proposed; our implementation on memory circuits show that we can tolerate variability effects enlarging the life of the memory more that 400%.
Advanced Fault-Tolerating architectures have also been investigated for technologies with very high variability and aging. This last stage of research has shown the counter intuitive principle that it is possible to improve reliability by introducing forced noise in the input lines of the architecture (Degradation Stochastic Resonance effect).